On the Positional Single Error Correction and Double Error Detection in Racetrack Memories

In the era of non-volatile memories, racetrack memory is a promising technology to pack hundreds bits in magnetic nanowire. A solid-state read head grown alongside nanowire sense individual which are pushed across by shifting force. However, probabilistic nature this movement inflicts positional errors. Therefore, robust and low-cost error correcting codes essential for reliable alternative on-chip memories storage applications. Recent works focus on Varshamov-Tenengolts (VT) can correct all single bit insertions deletions. VT incapable detecting multiple deletions/insertions. Because corrupts data words, multi-bit detection critical memories. article, we propose novel correction double (P-SECDED) code context with head. particular, adopt postamble-based approach where VT-encoded codeword appends carefully selected bit-pattern, stored racetrack. We rigorously analyze limitations postamble method, deduce criterion selection. further provide methodology optimize selection order single-bit errors as much two-bit possible. Finally, prove that incurable successfully detected. To best our knowledge, work first attempt P-SECDED fault-tolerance three-dimensional cannot afford heads.